The present invention generally relates to fabrication methods and resulting structures for semiconductor devices, and more specifically, to fabrication methods and resulting structures for a vertically stacked nanosheet CMOS (Complementary Metal Oxide Semiconductor) transistor architecture.
Traditional CMOS fabrication techniques include process flows for constructing planar transistors. With planar transistors, transistor density can be increased by decreasing the pitch between transistor gate elements. The ability to decrease the gate pitch for planar transistors is limited, however, by the required gate length and spacer thickness. In recent years, research has been devoted to the development of nonplanar transistor architectures. Some non-planar transistor architectures, such as vertical field effect transistors (VFETs) and nanosheet field effect transistors (NSFETs), employ semiconductor channels with various gate-all-around (GAA) technologies to achieve increased device density, greater power efficiency, and some increased performance over lateral devices. In a NSFET, the gate stack wraps around the full perimeter of each nanosheet, enabling fuller depletion in the channel region, and reducing short-channel effects due to steeper subthreshold swing (SS) and smaller drain induced barrier lowering (DIBL). The wrap-around gate structures and source/drain contacts used in nanosheet-based devices also enable greater management of leakage current and parasitic capacitance in the active regions, even as drive currents increase.